Method of fabricating semiconductor device
US10916561B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2019 |
| Grant date | Feb 9, 2021 |
| Priority date | — |
| Expiry date | Apr 3, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method is provided for forming a semiconductor device. The method includes forming a vertical film stack containing a sacrificial layer on a substrate and dielectric layers alternatingly and repeatedly stacked on the sacrificial layer, removing the sacrificial layer to form a horizontal channel above the substrate, depositing a conformal dielectric layer in the horizontal channel, etching trenches in the vertical film stack that connect to the horizontal channel. The method further includes removing the conformal dielectric layer from the horizontal channel, filling the horizontal channel and the trenches with a first electrically conductive material, removing the first electrically conductive material from the trenches, and filling the trenches with a second electrically conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.