Determining bias configuration for write operations in memory to improve device performance during normal operation as well as to improve the effectiveness of testing routines
US10923170B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 19, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Mar 19, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.