Low resistance contact for transistors
US10923575B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2019 |
| Grant date | Feb 16, 2021 |
| Priority date | — |
| Expiry date | Aug 21, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/021
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to an embodiment of the present invention, a method for forming contacts includes forming an oxide layer over and along a first liner layer. A first spacer layer is formed along the first liner layer opposing the oxide layer. A work function metal layer is formed along the first spacer layer opposing the first liner layer. A gate is formed on and along the work function metal opposing the first spacer. A second spacer layer is formed on the oxide layer. Portions of the oxide layer, the first liner layer, the first spacer, the work function metal layer and the second spacer layer are removed which forms a recess between the gate and the first spacer layer. A second liner layer is deposited in the recess. A low-resistance metal is deposited in the removed portions to form the first contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.