Multi-core communication acceleration using hardware queue device

US10929323B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Ren Wang · Portland, US
• Yipeng Wang · Houston, US
• Andrew J. Herdrich · Hillsboro, US
• Jr-Shian Tsai · Beaverton, US
• Tsung-Yuan C. Tai · Portland, US
• Niall D. McDonnell · Limerick, IE
• Hugh Wilkinson · Newton, US
• Bradley A. Burres · Waltham, US
• Bruce Richardson · Ottawa, CA
• Namakkal N. Venkatesan · Portland, US
• Debra Bernstein · Sudbury, US
• Edwin Verplanke · Chandler, US
• Stephen R. Van Doren · Portland, US
• An Yan · Sammamish, US
• Andrew Cunningham · Nottingham, GB
• David P. Sonnier · Austin, US
• Gage Eads · Austin, US
• James Clee · Orefield, US
• Jamison D. Whitesell · Allentown, US
• Jerry Pirog · Easton, US
• Jonathan Kenny · Tipperary, IE
• Joseph R. Hasting · Orefield, US
• Narender Vangati · Round Rock, US
• Stephen H. Miller · Naples, US
• Te K. Ma · Allentown, US
• William Burroughs · Macungie, US

Key dates

• Filing date: Oct 14, 2019
• Grant date: Feb 23, 2021
• Expiry date: Oct 14, 2039

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/6046
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.