Methods for fabricating a low-resistance interconnect
US10930551B2 · kind B2 · utility
2Cited by
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20Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 28, 2019 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuit devices and methods of forming the same are provided. A method according to the present disclosure includes providing a workpiece including a first metal feature in a dielectric layer and a capping layer over the first metal feature, selectively depositing a blocking layer over the capping layer, depositing an etch stop layer (ESL) over the workpiece, removing the blocking layer, and depositing a second metal feature over the workpiece such that the first metal feature is electrically coupled to the second metal feature. The blocking layer prevents the ESL from being deposited over the capping layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.