Chip arrangements

US10930614B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Manfred Mengel · Bad Abbach, DE
• Alexander Heinrich · Bad Abbach, DE
• Steffen ORSO · Reutlingen, DE
• Thomas Behrens · Madison, US
• Oliver Eichinger · Regensburg, DE
• Lim Fong · Melaka City, MY
• Evelyn Napetschnig · Diex, AT
• Edmund Riedl · Bergneustadt, DE

Key dates

• Filing date: Jul 26, 2017
• Grant date: Feb 23, 2021
• Expiry date: Oct 30, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/207
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip arrangement including a chip comprising a chip back side; a back side metallization on the chip back side, the back side metallization including a plurality of layers; a substrate comprising a surface with a metal layer; a zinc-based solder alloy configured to attach the back side metallization to the metal layer, the zinc-based solder alloy having by weight 8% to 20% aluminum, 0.5% to 20% magnesium, 0.5% to 20% gallium, and the balance zinc; wherein the metal layer is configured to provide a good wettability of the zinc-based solder alloy on the surface of the substrate. The plurality of layers may include one or more of a contact layer configured to contact a semiconductor material of the chip back side; a barrier layer; a solder reaction, and an oxidation protection layer configured to prevent oxidation of the solder reaction layer.