Method of manufacturing MOS transistor spacers
US10930757B2 · kind B2 · utility
0Cited by
3References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 20, 2018 |
| Grant date | Feb 23, 2021 |
| Priority date | — |
| Expiry date | Dec 20, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a MOS transistor includes forming a conductive first gate and forming insulating spacers along opposite sides of the gate, wherein the spacers are formed before the gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.