Semiconductor device with negative capacitance material in buried channel

US10937886B2 · kind B2 · utility

Assignee

• NANYA TECHNOLOGY CORPORATION · TW

Inventors

• Ching-Chia Huang · Taipei, TW
• Tseng-Fu Lu · New Taipei, TW
• Wei-Ming Liao · Taoyuan, TW

Key dates

• Filing date: Mar 11, 2019
• Grant date: Mar 2, 2021
• Expiry date: Jul 17, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/691

Abstract

A semiconductor device includes a substrate, at least one trench, an insulating layer, a lower metal layer, a negative capacitance material layer, and an upper metal layer. The trench has an inner surface in the substrate. The insulating layer is disposed on and lining the inner surface of the trench. The lower metal layer is disposed on the insulating layer and partially filling the trench. The negative capacitance material layer is disposed on and lining the insulating layer and the lower metal layer, in which a remained portion of the trench is defined by the negative capacitance material layer. The upper metal layer is disposed on the negative capacitance material layer and filling the remained portion of the trench.