Plating methods for modular and/or ganged waveguides for automatic test equipment for semiconductor testing
US10944148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 2016 |
| Grant date | Mar 9, 2021 |
| Priority date | — |
| Expiry date | Aug 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/0703
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Embodiments described herein perform incisions along the direction of the long axis of the waveguide, thereby exposing a trench structure which can be readily plated. Once divided and plated, the individual cut pieces can then be secured together to restore the original waveguide structure. In this fashion, multiple cut pieces can be secured together and used as “building blocks” to create a modular solution which can be used to provide a number of different customizable waveguide structures. Thus, embodiments described herein can perform plating procedures in a less expensive manner while achieving the benefits of ganged waveguide structures. Moreover, embodiments described herein can offer a modular approach to ganged waveguide design thereby allowing for end-user flexibility in testing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.