Removal of trilayer resist without damage to underlying structure
US10957536B2 · kind B2 · utility
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4References
13Claims
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Assignee
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Key dates
| Filing date | Nov 1, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Nov 1, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for semiconductor processing includes removing, from a first region of a semiconductor device, a middle layer and a bottom layer of a trilayer structure including a photoresist layer to expose at least one first structure. A top layer of the trilayer structure in a second region of the semiconductor device is removed during the removal of the bottom layer in the first region. The method further includes, after removing the middle and bottom layers in the first region, filling the first region to protect the at least one first structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.