Gate cut with high selectivity to preserve interlevel dielectric layer
US10957544B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 11, 2017 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | May 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/015
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for preserving interlevel dielectric in a gate cut region includes recessing a dielectric fill to expose cap layers of gate structures formed in a device region and in a cut region and forming a liner in the recess on top of the recessed dielectric fill. The liner includes a material to provide etch selectivity to protect the dielectric fill. The gate structures in the cut region are recessed to form a gate recess using the liner to protect the dielectric fill from etching. A gate material is removed from within the gate structure using the liner to protect the dielectric fill from etching. A dielectric gap fill is formed to replace the gate material and to fill the gate recess in the cut region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.