Method for forming a layer
US10957590B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Oct 30, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/535
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.