Semiconductor package and method of manufacturing the same
US10957654B2 · kind B2 · utility
3Cited by
0References
11Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 18, 2019 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Jan 18, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/15153
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Provided are a semiconductor package and a method of manufacturing the same, the semiconductor package including an interconnection part including an insulation layer and an interconnection layer, a semiconductor chip disposed on the interconnection part and electrically connected to the interconnection layer through a bonding pad, and an EMI shielding part connected to the interconnection layer while covering the semiconductor chip and the interconnection part.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.