Multi-layer encapsulation to enable endpoint-based process control for embedded memory fabrication
US10957850B2 · kind B2 · utility
4Cited by
17References
18Claims
0Family size
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Key dates
| Filing date | Oct 4, 2018 |
| Grant date | Mar 23, 2021 |
| Priority date | — |
| Expiry date | Oct 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/85
Abstract
A method for fabricating a semiconductor device includes forming a first encapsulation layer along the device, including forming the first encapsulation layer along a memory device region associated with a memory device, forming an intermediate layer on the first encapsulation layer to enable etch endpoint detection and endpoint-based process control for encapsulation layer etch back, and forming a second encapsulation layer on the intermediate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.