Vertical shared gate thin-film transistor-based charge storage memory

US10964701B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Abhishek A. Sharma · Hillsboro, US
• Van H. Le · Portland, US
• Gilbert Dewey · Beaverton, US
• Rafael Rios · Portland, US
• Jack T. Kavalieros · Portland, US
• Yih Wang · Portland, US
• Shriram Shivaraman · Hillsboro, US

Key dates

• Filing date: Mar 31, 2017
• Grant date: Mar 30, 2021
• Expiry date: Mar 31, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/31053
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A charge storage memory is described based on a vertical shared gate thin-film transistor. In one example, a memory cell structure includes a capacitor to store a charge, the state of the charge representing a stored value, and an access transistor having a drain coupled to a bit line to read the capacitor state, a vertical gate coupled to a word line to write the capacitor state, and a drain coupled to the capacitor to charge the capacitor from the drain through the gate, wherein the gate extends from the word line through metal layers of an integrated circuit.