Concurrent programming of multiple cells for non-volatile memory devices
US10978156B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 2018 |
| Grant date | Apr 13, 2021 |
| Priority date | — |
| Expiry date | Sep 22, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2216/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and methods are disclosed for concurrently programming non-volatile storage cells, such as those of an SLC NAND array. The non-volatile storage cells may be arranged into a first block comprising a first string of storage cells that intersects with a first word line at a first storage cell, a second block comprising a second string of storage cells that intersects with a second word line at a second storage cell, a bit line electrically connectable to the first string and the second string, and controller configured to apply a programming pulse, at an elevated voltage, to the first word line and second word line to concurrently program the first and second storage cells.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.