Reference circuits and methods for resistive memories
US10984861B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 10, 2018 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | Jul 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2013/0054
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device can include a plurality of memory cells formed in a substrate, each having a resistive element programmable between at least two different resistance states, including memory cells configured to store data received by the memory device, and reference cells; a reference circuit formed in the substrate configured to generate at least a first reference resistance from resistances of a plurality of reference cells; a sense circuit formed in the substrate coupled to the memory cells and at least the first reference resistance and configured to compare a resistance of a selected memory cell to at least the first reference resistance to determine the data stored by the selected memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.