Buried power and ground in stacked vertical transport field effect transistors
US10985064B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 29, 2019 |
| Grant date | Apr 20, 2021 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked semiconductor device structure and method for fabricating the same. The stacked semiconductor device structure includes a first vertical transport field effect transistor (VTFET) and a second VTFET stacked on the first VTFET. The structure further includes at least one power line and at least one ground line disposed within a backside of the stacked semiconductor structure. The method includes at least orientating a structure including a first VTFET and a second VTFET stacked on the first VTFET such that a multi-layer substrate, on which the first VTFET is formed, is above the first and second VTFETs. First and second contact trenches are formed through at least one layer of the multi-layer substrate. The first contact trench exposes a portion of a metal contact and the second contact trench exposes a portion of a source/drain region. The first and second contact trenches are filled with a contact material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.