Memory arrays and methods used in forming a memory array comprising strings of memory cells and operative through-array-vias

US10985179B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Yi Hu · Boise, US
• Merri L. Carlson · Boise, US
• Anilkumar Chandolu · Boise, US
• Indra V. Chary · Boise, US
• David Daycock · Boise, US
• Harsh Narendrakumar Jain · Boise, US
• Matthew J. King · Boise, US
• Jian Li · Boise, US
• Brett D. Lowe · Boise, US
• Prakash Rau Mokhna Rau · Boise, US
• Lifang Xu · Boise, US

Key dates

• Filing date: Aug 5, 2019
• Grant date: Apr 20, 2021
• Expiry date: Aug 5, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/037
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method used in forming a memory array comprising strings of memory cells and operative through-array-vias (TAVs) comprises forming a stack comprising vertically-alternating insulative tiers and conductive tiers. The stack comprises a TAV region and an operative memory-cell-string region. The TAV region comprises spaced operative TAV areas. Operative channel-material strings are formed in the stack in the operative memory-cell-string region and dummy channel-material strings are formed in the stack in the TAV region laterally outside of and not within the operative TAV areas. Operative TAVs are formed in individual of the spaced operative TAV areas in the TAV region. Other methods and structure independent of method are disclosed.