Control flow mechanism for execution of graphics processor instructions using active channel packing
US10990409B2 · kind B2 · utility
1Cited by
2References
19Claims
0Family size
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Key dates
| Filing date | Apr 21, 2017 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Apr 21, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T1/20
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.