Streaming interconnect architecture for data processing engine array

US10990552B1 · kind B1 · utility

Assignee

• XILINX, INC. · US

Inventors

• Goran H K Bilski · Mölndal, SE
• Peter McColgan · Dublin, IE
• Juan J. Noguera Serra · San Jose, US
• Baris Ozgul · Dublin, IE
• Jan Langer · Chemnitz, DE
• Richard L. Walke · Edinburgh, GB
• Ralph D. Wittig · Menlo Park, US
• Kornelis A. Vissers · Sunnyvale, US
• Philip B. James-Roxby · Longmont, US
• Christopher H. Dick · San Jose, US

Key dates

• Filing date: Apr 3, 2018
• Grant date: Apr 27, 2021
• Expiry date: Apr 29, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2213/0038
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Examples herein describe techniques for communicating between data processing engines in an array of data processing engines. In one embodiment, the array is a 2D array where each of the DPEs includes one or more cores. In addition to the cores, the data processing engines can include a memory module (with memory banks for storing data) and an interconnect which provides connectivity between the engines. To transmit processed data, a data processing engine identifies a destination processing engine in the array. Once identified, the data processing engine can transmit the processed data using a reserved point-to-point communication path in the interconnect that couples the source and destination data processing engines.