Method and memory used for reducing program disturbance by adjusting voltage of dummy word line

US10991438B1 · kind B1 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Yali Song · 红钢城街道, CN
• Jianquan Jia · 红钢城街道, CN
• Kaikai You · 红钢城街道, CN
• An Zhang · Kunshan, CN
• Xiangnan Zhao · 红钢城街道, CN
• Ying Cui · 红钢城街道, CN
• Shan Li · 红钢城街道, CN
• Kaiwei Li · 红钢城街道, CN
• Lei Jin · 红钢城街道, CN
• Xueqing Huang · 红钢城街道, CN
• Meng Lou · 红钢城街道, CN
• Jinlong Zhang · 红钢城街道, CN

Key dates

• Filing date: Feb 24, 2020
• Grant date: Apr 27, 2021
• Expiry date: Feb 24, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B43/27
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory includes an upper deck and a lower deck. The upper deck includes a first upper dummy word line. The lower deck includes a first lower dummy word line. A method for reducing program disturbance of the memory includes adjusting a first upper bias voltage applied to the first upper dummy word line and/or a first upper threshold voltage of the first upper dummy word line to adjust a first difference between the first upper bias voltage and the first upper threshold voltage; and adjusting a first lower bias voltage applied to the first lower dummy word line and/or a first lower threshold voltage of the first lower dummy word line to adjust a second difference between the first lower bias voltage and the first lower threshold voltage.