Source/drain contact depth control
US10991796B2 · kind B2 · utility
1Cited by
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10Claims
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Key dates
| Filing date | Dec 24, 2018 |
| Grant date | Apr 27, 2021 |
| Priority date | — |
| Expiry date | Dec 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0149
Abstract
A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.