Spacer-assisted lithographic double patterning
US10998193B1 · kind B1 · utility
2Cited by
7References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2020 |
| Grant date | May 4, 2021 |
| Priority date | — |
| Expiry date | Jan 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32139
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated chips and methods of forming the same include forming a first set of sidewall spacers on a first mandrel at first vertical level. The first mandrel is etched away. A second set of sidewall spacers is formed on a second mandrel at a second vertical level. A portion of the second set of sidewall spacers vertically overlaps with a portion of the first set of sidewall spacers. The second mandrel is etched away. A first hardmask layer is etched, using the vertically overlapping first set of sidewall spacers and second set of sidewall spacers as a mask.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.