Threshold voltage setting with boosting read scheme
US11004518B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2019 |
| Grant date | May 11, 2021 |
| Priority date | — |
| Expiry date | Jun 28, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods for reducing read disturb using NAND strings with poly-silicon channels and p-type doped source lines are described. During a boosted read operation for a selected memory cell transistor in a NAND string, a back-gate bias or bit line voltage may be applied to a bit line connected to the NAND string and a source line voltage greater than the bit line voltage may be applied to a source line connected to the NAND string; with these bias conditions, electrons may be injected from the bit line and annihilated in the source line during the read operation. To avoid leakage currents through NAND strings in non-selected memory blocks, the threshold voltages of source-side select gate transistors of the NAND strings may be set to a negative threshold voltage that has an absolute voltage value greater than the source line voltage applied during the read operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.