Patent · US Active

Level shift latch circuitry

US11005461B2 · kind B2 · utility

0Cited by

0References

8Claims

0Family size

Assignee

Arm Limited · GB

Inventors

Andy Wangkun Chen · Austin, US
Sai Sriharsha Manapragada · Austin, US
Yicong Li · Austin, US
Yew Keong Chong · Austin, US
Bikas Maiti · Austin, US
Sanjay Mangal · Austin, US
Hsin-Yu Chen · Austin, US

Key dates

Filing date	Jun 8, 2018
Grant date	May 11, 2021
Priority date	—
Expiry date	Jun 8, 2038

Classification

Technology area (CPC H)Electricity
CPC primaryH03K17/223
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Various implementations described herein are directed to an integrated circuit having first devices arranged to operate as a latch. The first devices may include inner devices and outer devices. The integrated circuit may include second devices coupled to the first devices and arranged to operate as a level shifter. The second devices may include upper devices and lower devices. The lower devices may be cross-coupled to gates of the inner devices and the upper devices. The integrated circuit may include input signals applied to gates of the outer devices and the lower devices to thereby generate output signals from the outputs of the lower devices that are applied to the gates of the inner devices and the upper devices to activate latching of the output signals.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.