Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer
US11011425B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2019 |
| Grant date | May 18, 2021 |
| Priority date | — |
| Expiry date | Jul 29, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0144
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of production of a 3D microelectronic device includes assembling a structure comprising a lower level with a component partially formed in a first semiconductor layer with a support provided with a second semiconductor layer in which a transistor channel of an upper level is capable of being produced, the second semiconductor layer being capped with a dielectric material layer capable of forming a gate dielectric, forming a capping layer arranged on the dielectric material layer, and potentially capable of forming a lower gate portion of the transistor, and defining a gate dielectric zone and an active zone of said transistor by etching the dielectric material layer and the second semiconductor layer, the capping layer protecting said dielectric material layer during this etching.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.