Method for patterning a semiconductor structure
US11018006B2 · kind B2 · utility
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18References
9Claims
0Family size
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Key dates
| Filing date | Oct 4, 2019 |
| Grant date | May 25, 2021 |
| Priority date | — |
| Expiry date | Dec 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for patterning a semiconductor structure is provided, including forming an additional third material layer on a thinner portion of a second material layer to be an etching buffer layer. The removed thickness of the thinner portion of the second material layer covered by the third material layer during an etching back process is therefore reduced.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.