Systems and methods for selectively bypassing address-generation hardware in processor instruction pipelines
US11023241B2 · kind B2 · utility
0Cited by
3References
25Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 21, 2018 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Dec 13, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3867
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems and methods selectively bypass address-generation hardware in processor instruction pipelines. In an embodiment, a processor includes an address-generation stage and an address-generation-bypass-determination unit (ABDU). The ABDU receives a load/store instruction. If an effective address for the load/store instruction is not known at the ABDU, the ABDU routes the load/store instruction via the address-generation stage of the processor. If, however, the effective address of the load/store instruction is known at the ABDU, the ABDU routes the load/store instruction to bypass the address-generation stage of the processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.