Chip to chip interface with scalable bandwidth
US11023403B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 2, 2019 |
| Grant date | Jun 1, 2021 |
| Priority date | — |
| Expiry date | Dec 2, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/17325
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A system and method for efficiently transporting data across lanes. A computing system includes an interconnect with lanes for transporting data between a source and a destination. When a source receives an indication of a bandwidth requirement change from a first data rate to a second data rate, the transmitter in the source sends messages to the receiver in the destination. The messages indicate that the data rate is going to change and reconfiguration of one or more lanes will be performed. The transmitter selects one or more lanes for transporting data at the second data rate. The transmitter maintains data transport at the first data rate while reconfiguring the selected one or more lanes to the second data rate. After completing the reconfiguration, the transmitter transports data at the second data rate on the selected one or more lanes while preventing data transport on any unselected lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.