Memory device detecting an error in write data during a write operation, memory system including the same, and operating method of memory system
US11030040B2 · kind B2 · utility
2Cited by
6References
19Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 5, 2018 |
| Grant date | Jun 8, 2021 |
| Priority date | — |
| Expiry date | Nov 8, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a write error check circuit suitable for detecting an error in received data using an error correction code during a write operation; and a memory core suitable for storing the received data and the received error correction code when no error is detected by the write error check circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.