Mid-level instruction cache
US11036643B1 · kind B1 · utility
3Cited by
10References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 29, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | May 29, 2039 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/452
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.