Multiple patterning with self-alignment provided by spacers
US11037821B2 · kind B2 · utility
2Cited by
5References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 1, 2019 |
| Grant date | Jun 15, 2021 |
| Priority date | — |
| Expiry date | Jun 17, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods of forming interconnects and structures for interconnects. A hardmask layer is patterned to form a plurality of first trenches arranged with a first pattern, and sidewall spacers are formed inside the first trenches on respective sidewalls of the hardmask layer bordering the first trenches. An etch mask is formed over the hardmask layer. The etch mask includes an opening exposing a portion of the hardmask layer between a pair of the sidewall spacers. The portion of the hardmask layer exposed by the opening in the etch mask is removed to define a second trench in the hardmask layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.