Additive patterning of semiconductor film stacks

US11049537B2 · kind B2 · utility

Assignee

• Applied Materials, Inc. · US

Inventors

• John O. Dukovic · Pleasantville, US
• Srinivas D. Nemani · Sunnyvale, US
• Ellie Yieh · San Jose, US
• Praburam Gopalraja · San Jose, US
• Steven Hiloong WELCH · Milpitas, US
• Bhargav S. Citla · Fremont, US

Key dates

• Filing date: Jul 29, 2019
• Grant date: Jun 29, 2021
• Expiry date: Jul 29, 2039

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N50/85
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

One or more embodiments described herein generally relate to patterning semiconductor film stacks. Unlike in conventional embodiments, the film stacks herein are patterned without the need of etching the magnetic tunnel junction (MTJ) stack. Instead, the film stack is etched before the MTJ stack is deposited such that the spin on carbon layer and the anti-reflective coating layer are completely removed and a trench is formed within the dielectric capping layer and the oxide layer. Thereafter, MTJ stacks are deposited on the buffer layer and on the dielectric capping layer. An oxide capping layer is deposited such that it covers the MTJ stacks. An oxide fill layer is deposited over the oxide capping layer and the film stack is polished by chemical mechanical polishing (CMP). The embodiments described herein advantageously result in no damage to the MTJ stacks since etching is not required.