Universal process kit
US11049760B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2017 |
| Grant date | Jun 29, 2021 |
| Priority date | — |
| Expiry date | Mar 26, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldElectrical machinery, apparatus, energy
- WIPO sectorElectrical engineering
Abstract
The implementations described herein generally relate to a process kit suitable for use in a semiconductor process chamber, which reduces edge effects and widens the processing window with a single edge ring as compared to conventional process kits. The process kit generally includes an edge ring disposed adjacent to and surrounding a perimeter of a semiconductor substrate in a plasma chamber. A dimension of a gap between the substrate and the edge ring is less than about 1000 μm, and a height difference between the substrate and the edge ring is less than about (+/−) 300 μm. The resistivity of the ring is less than about 50 Ohm-cm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.