Olivier Joubert
30Patents
8h-index
67Co-inventors
78Inventor score
Filing activity: Jun 23, 1998 → Nov 10, 2022
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| USD797691S1 | Composite edge ring | General | 45 | Active |
| US10312048B2 | Creating ion energy distribution functions (IEDF) | Electricity | 39 | Active |
| US10685807B2 | Creating ion energy distribution functions (IEDF) | Electricity | 32 | Active |
| US6271144A | Process for etching a polycrystalline Si(1-x)Ge(x) layer or a stack of polycrystalline Si(1-x)Ge(x) layer and of a polycrystalline Si layer, and its application to microelectronics | Electricity | 18 | Expired |
| US9570317B2 | Microelectronic method for etching a layer | Electricity | 11 | Active |
| US6326302A | Process for the anisotropic etching of an organic dielectric polymer material by a plasma gas and application in microelectronics | Electricity | 8 | Expired |
| US9378970B2 | Plasma etching process | Electricity | 8 | Active |
| US9257293B2 | Methods of forming silicon nitride spacers | Electricity | 8 | Active |
| US6238844A | Process for depositing a plasma polymerized organosilicon photoresist film | Electricity | 6 | Expired |
| US9975758B2 | Wafer processing equipment having exposable sensing layers | Performing Operations; Transporting | 6 | Active |
| US9725302B1 | Wafer processing equipment having exposable sensing layers | Performing Operations; Transporting | 5 | Active |
| US6589715B2 | Process for depositing and developing a plasma polymerized organosilicon photoresist film | Electricity | 5 | Expired |
| US6818488B2 | Process for making a gate for a short channel CMOS transistor structure | Electricity | 4 | Expired |
| US9583339B2 | Method for forming spacers for a transistor gate | Electricity | 3 | Active |
| US11069504B2 | Creating ion energy distribution functions (IEDF) | Electricity | 3 | Active |
| US10062602B2 | Method of etching a porous dielectric material | Electricity | 3 | Active |
| US10056266B2 | Method for manufacturing a resistive device for a memory or logic circuit | Electricity | 3 | Active |
| US8546263B2 | Method of patterning of magnetic tunnel junctions | Electricity | 3 | Active |
| US9059400B2 | Magnetic random access memory cells with isolating liners | Electricity | 2 | Active |
| US11728124B2 | Creating ion energy distribution functions (IEDF) | Electricity | 2 | Active |
| US8956886B2 | Embedded test structure for trimming process control | Electricity | 2 | Active |
| US9818621B2 | Cyclic oxide spacer etch process | Electricity | 2 | Active |
| US7723610B2 | Titanium oxide-based sol-gel polymer | Chemistry; Metallurgy | 0 | Active |
| US12237149B2 | Reducing aspect ratio dependent etch with direct current bias pulsing | Electricity | 0 | Active |
| US11208354B2 | Sintered zirconia mullite refractory composite, methods for its production and use thereof | Chemistry; Metallurgy | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.