Three-dimensional memory device
US11069712B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 22, 2020 |
| Grant date | Jul 20, 2021 |
| Priority date | — |
| Expiry date | Jul 22, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A three-dimensional (3D) memory device is provided. The 3D memory device includes a substrate, an alternating conductive/dielectric stack, an epitaxial layer, and a vertical structure. The alternating conductive/dielectric stack is disposed on the substrate. The alternating conductive/dielectric stack includes a plurality of dielectric layers and a plurality of conductive layers alternately stacked in a vertical direction perpendicular to a surface of the substrate. The epitaxial layer is disposed between the substrate and the alternating conductive/dielectric stack in the vertical direction. The vertical structure penetrates the alternating conductive/dielectric stack in the vertical direction for being partly disposed in the epitaxial layer. The epitaxial layer includes a protruding part disposed between the vertical structure and a bottom dielectric layer of the alternating conductive/dielectric stack in a horizontal direction orthogonal to the vertical direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.