Tungsten feature fill

US11075115B2 · kind B2 · utility

Assignee

• Novellus Systems, Inc. · US

Inventors

• Anand Chandrashekar · Sunnyvale, US
• Esther Jeng · Los Altos, US
• Raashina Humayun · Los Altos, US
• Michal Danek · Cupertino, US
• Juwen Gao · San Jose, US
• Deqi Wang · San Jose, US

Key dates

• Filing date: Sep 6, 2018
• Grant date: Jul 27, 2021
• Expiry date: Sep 6, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76865
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Described herein are methods of filling features with tungsten and related systems and apparatus. The methods include inside-out fill techniques as well as conformal deposition in features. Inside-out fill techniques can include selective deposition on etched tungsten layers in features. Conformal and non-conformal etch techniques can be used according to various implementations. The methods described herein can be used to fill vertical features, such as in tungsten vias, and horizontal features, such as vertical NAND (VNAND) word lines. Examples of applications include logic and memory contact fill, DRAM buried word line fill, vertically integrated memory gate/word line fill, and 3-D integration with through-silicon vias (TSVs).