Stacked transistor assembly with dual middle mounting clips
US11075148B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 6, 2019 |
| Grant date | Jul 27, 2021 |
| Priority date | — |
| Expiry date | Nov 6, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A stacked assembly of semiconductor devices includes a mounting pad covering a first portion of a low-side semiconductor device, and a contact layer covering a second portion of the low-side semiconductor device. A first mounting clip electrically connected to the contact layer has a supporting portion joining the first mounting clip to a first lead frame portion. A second mounting clip attached to the mounting pad has a supporting portion joining the second mounting clip to a second lead frame portion. A high-side semiconductor device has a first terminal electrically connected to the first mounting clip and thereby to the contact layer, and a second terminal electrically connected to the second mounting clip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.