Method of forming split gate memory cells
US11081553B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 6, 2020 |
| Grant date | Aug 3, 2021 |
| Priority date | — |
| Expiry date | May 6, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6891
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a memory device includes forming a second insulation layer on a first conductive layer formed on a first insulation layer formed on semiconductor substrate. A trench is formed into the second insulation layer extending down and exposing a portion of the first conductive layer, which is etched or oxidized to have a concave upper surface. Two insulation spacers are formed along sidewalls of the trench, having inner surfaces facing each other and outer surfaces facing away from each other. A source region is formed in the substrate between the insulation spacers. The second insulation layer and portions of the first conductive layer are removed to form floating gates under the insulation spacers. A third insulation layer is formed on side surfaces of the floating gates. Two conductive spacers are formed along the outer surfaces. Drain regions are formed in the substrate adjacent the conductive spacers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.