Defect correction on metal resists
US11094543B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 4, 2020 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Dec 4, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/32136
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming a semiconductor device includes depositing a metal resist layer over a layer to be patterned that is formed over a substrate; patterning the metal resist layer using a lithography process to form a patterned metal resist layer and expose portions of the layer to be patterned; selectively depositing a silicon containing layer over the patterned resist layer by exposing the substrate to a gas mixture comprising a silicon precursor, the silicon containing layer being preferentially deposited over a top surface of the metal resist layer; and performing a surface cleaning process by exposing the layer to be patterned and the patterned metal resist layer covered with the silicon containing layer to a plasma process with an etch chemistry comprising a halogen or hydrogen.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.