Interconnection structure of selective deposition process
US11094588B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Oct 10, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53257
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure generally relate an interconnect structure formed on a substrate and a method of forming the interconnect structure thereon. In one embodiment, a method of forming an interconnect structure includes forming an opening comprising a via and a trench in an insulating structure formed on a substrate, forming a first passivation layer in the opening, removing a portion of the first passivation layer from the opening, and selectively depositing a first metal containing material in the via.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.