Composite IC chips including a chiplet embedded within metallization layers of a host IC chip
US11094672B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 27, 2019 |
| Grant date | Aug 17, 2021 |
| Priority date | — |
| Expiry date | Sep 27, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Composite IC chip including a chiplet embedded within metallization levels of a host IC chip. The chiplet may include a device layer and one or more metallization layers interconnecting passive and/or active devices into chiplet circuitry. The host IC may include a device layer and one or more metallization layers interconnecting passive and/or active devices into host chip circuitry. Features of one of the chiplet metallization layers may be directly bonded to features of one of the host IC metallization layers, interconnecting the two circuitries into a composite circuitry. A dielectric material may be applied over the chiplet. The dielectric and chiplet may be thinned with a planarization process, and additional metallization layers fabricated over the chiplet and host chip, for example to form first level interconnect interfaces. The composite IC chip structure may be assembled into a package substantially as a monolithic IC chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.