Vertical two-transistor single capacitor memory cells and memory arrays

US11094697B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Gloria Yang · Boise, US
• Suraj Mathew · Boise, US
• Raghunath Singanamalla · Boise, US
• Vinay Nair · Boise, US
• Scott J. Derner · Boise, US
• Michael A. Shore · Boise, US
• Brent Keeth · Boise, US
• Fatma Arzum Simsek-Ege · Boise, US
• Diem Thy N. Tran · Garden City, US

Key dates

• Filing date: Nov 7, 2018
• Grant date: Aug 17, 2021
• Expiry date: Nov 7, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D88/00
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Some embodiments include a memory cell having first and second transistors, and a capacitor vertically displaced relative to the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes. Some embodiments include a memory cell having first and second transistors vertically displaced relative to one another, and a capacitor between the first and second transistors. The capacitor has a first node electrically coupled with a source/drain region of the first transistor, a second node electrically coupled with a source/drain region of the second transistor, and capacitor dielectric material between the first and second nodes.