Performance of a bit flipping (BF) decoder of an error correction system
US11108407B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 9, 2020 |
| Grant date | Aug 31, 2021 |
| Priority date | — |
| Expiry date | Mar 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/112
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are described for improving the decoding latency and throughput of an error correction system that includes a bit flipping (BF) decoder, where the BF decoder uses a bit flipping procedure. In an example, different decoding parameters are determined including any of a decoding number of a decoding iteration, a checksum of a codeword, a degree of a variable node, and a bit flipping threshold defined for the bit flipping procedure. Based on one or more of these decoding parameters, a decision can be generated to skip the bit flipping decoding procedure, thereby decreasing the decoding latency and increasing the decoding throughput. Otherwise, the bit flipping decoding procedure can be performed to compute a bit flipping energy and determine whether particular bits are to be flipped or not. Hence, the overall performance (e.g., bit error rate) is not significantly impacted.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.