Testing of bonded wafers and structures for testing bonded wafers
US11119146B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 19, 2020 |
| Grant date | Sep 14, 2021 |
| Priority date | — |
| Expiry date | Aug 19, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/34
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Examples described herein generally relate to testing of bonded wafers and structures implemented for such testing. In an example method, power is applied to a first pad on a stack of bonded wafers. A wafer of the stack includes a process control monitor (PCM) region that includes structure regions. Each structure region is a device under test region, dummy region, and/or chain interconnect region (CIR). The stack includes a serpentine chain test structure (SCTS) electrically connected between first and second metal features in the wafer in first and second CIRs, respectively, in the PCM region. The SCTS includes segments, one or more of which are disposed between neighboring structure regions in the PCM region that are not the first and second CIRs. A signal is detected from a second pad on the stack. The first and second pads are electrically connected to the first and second metal features, respectively.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.