Through plate interconnect for a vertical MIM capacitor

US11121073B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Travis W. Lajoie · Forest Grove, US
• Abhishek A. Sharma · Hillsboro, US
• Juan G. Alzate-Vinasco · Tigard, US
• Chieh-Jen Ku · Hillsboro, US
• Shem Ogadhoh · Beaverton, US
• Allen B. Gardiner · Portland, US
• Blake C. Lin · Portland, US
• Yih Wang · Portland, US
• Pei-Hua Wang · Beaverton, US
• Jack T. Kavalieros · Portland, US
• Bernhard Sell · Dresden, DE
• Tahir Ghani · Portland, US

Key dates

• Filing date: Apr 2, 2018
• Grant date: Sep 14, 2021
• Expiry date: Jan 14, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B12/315
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

An interconnect structure is disclosed. The interconnect structure includes a first metal interconnect in a bottom dielectric layer, a via that extends through a top dielectric layer, a metal plate, an intermediate dielectric layer, and an etch stop layer, and a metal in the via to extend through the top dielectric layer, the metal plate, the intermediate dielectric layer and the etch stop layer to the top surface of the first metal interconnect. The metal plate is coupled to an MIM capacitor that is parallel to the via. The second metal interconnect is on top of the metal in the via.