Memory device with configurable error correction modes
US11126498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 17, 2020 |
| Grant date | Sep 21, 2021 |
| Priority date | — |
| Expiry date | Feb 17, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0411
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatus to selectively implement single-error correcting (SEC) operations or single-error correcting and double-error detecting (SECDED) operations, without noticeably impacting die size, for information received from a host device. For example, a host device may indicate that a memory system is to implement SECDED operations using one or more communications (e.g., messages). In another example, the memory system may be hardwired to perform SECDED for certain options. The memory system may adapt circuitry associated with SEC operations to implement SECDED operations without noticeably impacting die size. To implement SECDED operations using SEC circuitry, the memory system may include some additional circuitry to repurpose the SEC circuitry for SECDED operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.