Barrier for power metallization in semiconductor devices

US11127693B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Johann Gatterbauer · Parsberg, DE
• Katrin Albers · Regensburg, DE
• Joerg Busch · Regensburg, DE
• Klaus Goller · Dresden, DE
• Norbert Mais · Nuremberg, DE
• Marianne Kolitsch · Villach, AT
• Michael Nelhiebel · Villach, AT
• Rainer Pelzer · Wernberg, AT
• Bernhard Weidgans · Bernhardswald, DE

Key dates

• Filing date: Dec 11, 2019
• Grant date: Sep 21, 2021
• Expiry date: Mar 24, 2040

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/3512
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A semiconductor device includes a structured interlayer on a substrate, a structured power metallization on the structured interlayer, and a barrier on the structured power metallization. The barrier is configured to prevent diffusion of at least one of water, water ions, sodium ions, potassium ions, chloride ions, fluoride ions, and sulphur ions towards the structured power metallization. A first defined edge of the structured interlayer faces the same direction as a first defined edge of the structured power metallization and extends beyond the first defined edge of the structured power metallization by at least 0.5 microns. The structured interlayer has a compressive residual stress at room temperature and the structured power metallization generates a tensile stress at room temperature that is at least partly counteracted by the compressive residual stress of the structured interlayer. The first defined edge of the structured power metallization has a sidewall which slopes inward.