Energy efficient processor core architecture for image processor
US11138013B2 · kind B2 · utility
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43References
20Claims
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Key dates
| Filing date | Aug 24, 2020 |
| Grant date | Oct 5, 2021 |
| Priority date | — |
| Expiry date | Aug 24, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N3/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus that includes a program controller to fetch and issue instructions is described. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.